This present invention relates to digital circuits. More specifically, it relates to delay locked loop design.
Accurate high-speed clock signals are often used for transmitting and receiving data in high-speed circuits, such as high-speed memory devices or high speed bus channels. However, high speed clock signals often become distorted during transmission and reception. Consequently, high speed circuits, such as dynamic random access memory (DRAM) devices, often recover an externally provided high-speed clock signal by locking an accurate internally generated clock signal to the distorted externally provided clock signal.
A delayed locked loop (DLL) is typically used to delay the internally generated clock signal in order to match the phase of the internally generated clock signal to the phase of some reference clock signal. Typically, a phase-detection circuit in the DLL compares the phase of the internal clock signal to the reference signal and a control-logic block that is coupled to the output of the phase-detection circuit is used to increase or decrease a delay produced by a chain of delay elements used to delay the internal clock signal. U.S. Pat. Nos. 5,945,862 and 6,125,157 to Donnelly et al. represent two approaches to locking an internal clock signal to an external clock signal using delay elements.
It is desirable to provide for a fully digital DLL circuit that can be fabricated using standard digital design techniques.
In accordance with a first aspect of the present invention, a circuit for selectively delaying a reference clock signal is provided. The circuit includes a phase splitter coupled to a first delay line and a second delay line. Each delay line includes a set of output taps and has a multiplexor that is selectively coupled to the output taps. An output of each multiplexor is coupled to a latch. The latch provides an output clock signal, which may be fed back to a phase detector, where the phase detector also receives an input clock signal. A controller is coupled to the phase detector and, depending upon the output of the phase detector, provides control signals to each multiplexor.
In a preferred embodiment, the circuit is implemented using standard digital design techniques.
In accordance with a second aspect of the present invention, a method for recovering a clock signal from an input clock signal is provided. The method includes converting a reference clock signal into an in-phase reference and a complementary reference, and selectively delaying the in-phase reference and the complementary reference. The method further includes generating an output clock signal from the selected in-phase reference and the selected complementary reference.
In accordance with the preferred embodiment, the selective delay of the in-phase reference and the complementary reference is based upon a difference signal determined by comparing an input clock signal with a feedback clock signal, where the feedback clock signal is related to the output clock signal.
In accordance with another embodiment, the method is implemented using digital design techniques.
This summary is not intended to be all-inclusive, but rather illustrative. These and other aspects of the present invention, and its various embodiments, are described in greater detail below.